| abstract |
A power supply compensation capacitor is formed by utilizing an empty space in a wiring layer. A plurality of memory mats MAT arranged in the Y direction, a sense area SA arranged between memory mats MAT adjacent in the Y direction, a column decoder 13 for generating a column selection signal, and a plurality of memories A column selection line YS that extends in the Y direction on the mat MAT and supplies a column selection signal from the column decoder 13 to the plurality of sense areas SA, and a power supply compensation provided on the memory mat MATa farthest from the column decoder 13 And a capacitor 30. The power supply compensation capacitor 30 includes power supply wirings VL1 and VL2 that function as capacitive electrodes, and at least one of them is formed in the same wiring layer as the column selection line YS. According to the present invention, since the power supply compensation capacitor 30 is provided on the memory mat MATa that does not require the column selection line YS, the chip area can be reduced. [Selection] Figure 7 |