http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2012160244-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f8e7780b6442925fa39eee8382aa6c9f |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0425 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-24 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-04 |
| filingDate | 2011-02-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3381c543ad8e09abecdc1a5adb1ba5ea |
| publicationDate | 2012-08-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2012160244-A |
| titleOfInvention | Semiconductor non-volatile memory |
| abstract | A semiconductor nonvolatile memory capable of preventing erroneous data writing is provided. A high voltage source voltage is applied to the source region of each memory cell 10 to which data of a first logic level is to be written, and a low voltage is applied to the drain region. Is applied to cause a write current to flow in the memory cell 10. On the other hand, a high source voltage is applied to the source region and a write inhibit voltage higher than the power supply voltage VDD is applied to the drain region for the memory cell 10 to which data of the second logic level is to be written. As a result, the write current is inhibited from flowing into the memory cell 10. [Selection] Figure 3 |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9472282-B2 |
| priorityDate | 2011-02-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID657275 http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID447483815 |
Total number of triples: 16.