| abstract |
The performance of a semiconductor device is improved. An element isolation region is formed of a silicon oxide film embedded in a trench, and an upper portion protrudes from a semiconductor substrate. On the side wall of the element isolation region that protrudes from the semiconductor substrate, Sidewall insulating film SW1 made of silicon nitride or silicon oxynitride is formed. The gate insulating film of the MISFET is composed of an Hf-containing insulating film 5 containing hafnium, oxygen, and an element for lowering the threshold as main components. The gate electrode GE, which is a metal gate electrode, includes the active region 14 and the sidewall insulating film. The film SW1 and the element isolation region 13 are extended. The element for lowering the threshold value is rare earth or Mg in the case of an n-channel type MISFET, and Al, Ti, or Ta in the case of a p-channel type MISFET. [Selection] Figure 25 |