http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2011234352-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fdf3b6ced3d7710ec0bc0addb67a1cc9 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K3-356 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K23-44 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K23-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K21-406 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K21-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-786 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K23-54 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-0175 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K23-44 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-20 |
| filingDate | 2011-04-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_33cf1585f13517d8da13d041017ff8b6 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_204da3b600d306d80fbf3e15f5834778 |
| publicationDate | 2011-11-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2011234352-A |
| titleOfInvention | Frequency divider circuit |
| abstract | An operation failure of a frequency divider circuit is suppressed. A shift register that generates and outputs 2 × X (X is a natural number of 2 or more) pulse signals according to a first or second clock signal, and a first register according to 2 × X pulse signals. A divided signal output circuit that generates and outputs a signal that becomes a third clock signal having a period X times the period of the clock signal, and the divided signal output circuit includes 2 × Controls whether or not the first to Xth pulse signals of the X number of pulse signals are inputted with different pulse signals and the voltage of the signal that becomes the third clock signal is set to the first voltage. Different pulse signals from the (X + 1) th to 2 × Xth pulse signals in the 2 × X pulse signals are input to the X first transistors and the gates, respectively, and the third clock Signal voltage to be signal And X second transistors for controlling whether or not to be set to the second voltage. [Selection] Figure 1 |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2020167419-A |
| priorityDate | 2010-04-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 53.