| abstract |
A semiconductor memory device capable of stably reading data with a sense amplifier without increasing the circuit scale or control lines. A semiconductor memory device controls a sense amplifier, a plurality of memory cell arrays, a shared MOS transistor for connecting or disconnecting bit lines included in the sense amplifier and the memory cell array, and an operation of the shared MOS transistor. Control circuit. Part or all of the sense amplifier bit lines, which are bit lines connecting the sense amplifiers and the shared MOS transistors, are embedded in a semiconductor substrate. [Selection] Figure 1 |