| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6b822ee046eb6c45d1e3bd9ce9c1782e |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-70
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-02 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1203
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-84
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8258
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7869
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K3-356008
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K3-35606
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1255
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1225
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-1733
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0688
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C14-0063 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C19-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K3-037
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K3-356
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-04 |
| filingDate |
2010-12-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8bb761a089dba691e10fe050a316ea73
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_01586b738d5c3da823a8b306e0b71efa |
| publicationDate |
2011-07-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2011147121-A |
| titleOfInvention |
Nonvolatile latch circuit, logic circuit, and semiconductor device using the same |
| abstract |
A novel nonvolatile latch circuit and a semiconductor device using the same are provided. An output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element through a second transistor. A latch circuit having a loop structure using a transistor using an oxide semiconductor as a semiconductor material constituting a channel formation region as a switching element and electrically connected to a source electrode or a drain electrode of the transistor The data of the latch circuit can be held. Thus, a nonvolatile latch circuit can be configured. [Selection] Figure 1 |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2013207395-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2014207667-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-7350962-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2019068080-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2014075785-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2013243353-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2018117158-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2020167429-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2020202005-A |
| priorityDate |
2009-12-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |