http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2011071243-A

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filingDate 2009-09-24-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cb3f609919e59a75d12d070d16367e0c
publicationDate 2011-04-07-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2011071243-A
titleOfInvention Semiconductor device and manufacturing method thereof
abstract A semiconductor device for simultaneously forming a MOS transistor having a relatively thick gate insulating film and a MOS transistor having a relatively thin gate insulating film, and a method for manufacturing the same. An inversion formed under a field insulating film by covering a field insulating film end in a region where a MOS transistor having a relatively thin gate insulating film is formed with a relatively thick gate insulating film. By offsetting the channel region 33 of the MOS transistor having the relatively thin gate insulating film 25 from the prevention diffusion layer 31, the film thickness variation of the field insulating film and the etching variation of the relatively thick first gate insulating film 24, In addition, a semiconductor device having stable element characteristics that can suppress the influence of the narrow channel effect generated when the channel width of the MOS transistor is designed to be short without being affected by the concentration fluctuation of the channel end due to the inversion preventing diffusion layer. [Selection] Figure 3
priorityDate 2009-09-24-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H08293598-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2006278633-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H04297063-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2004228336-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2010027688-A
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Total number of triples: 23.