http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2010251529-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_294881271413951a95f284b588a68e66 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0629 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-245 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-826 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-011 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-8416 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-101 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-8833 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-8825 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-80 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-8822 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-30 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L49-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L45-00 |
| filingDate | 2009-04-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_90f3744d549fbe22f0ab7b747038072a |
| publicationDate | 2010-11-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2010251529-A |
| titleOfInvention | Semiconductor memory device and manufacturing method thereof |
| abstract | A semiconductor memory device and a method for manufacturing the same are provided, which can reduce the wiring resistance between a selection transistor and a resistance change element and stably perform an erase operation of the resistance change element. A first MOS transistor 2 formed on a semiconductor substrate 11 and a first diffusion layer 17A formed on the semiconductor substrate 11 and having two first diffusion layers 16A and 17A of the first MOS transistor 2 are shared. The second MOS transistor 3 serving as a diffusion layer, and the first and second sidewall insulating films 15A and 15B are interposed between the first gate electrode 13A of the first MOS transistor 2 and the second gate electrode 13B of the second MOS transistor 3. The variable resistance element 4 is formed and connected to the common diffusion layer 18. The resistance change layer 22 includes a memory layer 24 made of a metal oxide film and an ion source layer 25 that supplies metal ions to the memory layer 24 or receives metal ions supplied to the memory layer 24. [Selection] Figure 1 |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-5807789-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2012105139-A1 |
| priorityDate | 2009-04-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 72.