| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f56b5174f7d196258707ccf1d609796e |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823807
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823814
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823835
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7843 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-522
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-092
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate |
2009-03-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8ecc76a05576f671313de1e9a850ca33
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_352d83adaf26cac8cab4666136b0e8e5
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d05cec8836ae081d1a8f5d5954dc9fdd
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4306049fb742ad0f74f6c8ef32c04622
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f3e53ae8717f1a691fdd420b96bf379e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3e4ed3d6d587c84d4587ad186adba963
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e54ad4687b93b9215dc48babeaf42fff
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1591af904dbbe0f53e7060d099d1569c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6e73f7359a5a5d1639f0201e72492021 |
| publicationDate |
2010-09-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2010212388-A |
| titleOfInvention |
Semiconductor device and manufacturing method thereof |
| abstract |
The performance of a semiconductor device is improved. An n + type semiconductor region 7b for source / drain of an n channel MISFET Qn and a gate electrode GE1 formed on a semiconductor substrate 1, and a p + type semiconductor region 8b for source / drain of a p channel MISFET Qp and A metal silicide layer 13b made of nickel platinum silicide is formed on the gate electrode GE2 by a salicide process. Thereafter, after forming the tensile stress film TSL1 on the entire surface of the semiconductor substrate 1, the tensile stress film TSL1 on the p-channel type MISFET Qp is removed by dry etching, and the compressive stress film CSL1 is formed on the entire surface of the semiconductor substrate 1. The compressive stress film CSL1 on the n-channel type MISFET Qn is removed by dry etching. The Pt concentration in the metal silicide layer 13b is the highest on the surface and decreases as the position becomes deeper from the surface. [Selection] Figure 17 |
| priorityDate |
2009-03-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |