http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2010211920-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f56b5174f7d196258707ccf1d609796e |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-403 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-406 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-407 |
| filingDate | 2010-05-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a3f4e86d363e44055375975948f98452 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_38931828a98d300def84b05efc619ef1 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ff5b41c9ecd1ce64e5058430ae429e8d |
| publicationDate | 2010-09-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2010211920-A |
| titleOfInvention | Semiconductor memory device |
| abstract | A semiconductor memory device that internally sets latency at an appropriate timing is provided. A trigger generation circuit outputs a trigger signal. The delay circuit 110 receives the trigger signal and outputs a delay signal obtained by delaying the trigger signal. The clock counter 106 receives the clock, counts the number of received clocks from when the trigger signal is received until it receives the delay signal, and outputs the count result. The determination circuit 107 stores the correspondence between the number of clocks and the latency, and determines the latency corresponding to the count result output from the clock counter. The latency register 108 holds the determined latency. The WAIT control circuit 109 outputs a WAIT signal to the outside based on the latency held in the latency register 108. [Selection] Figure 1 |
| priorityDate | 2010-05-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 59.