| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_a7b097bfd3f350ed27ffa53e1f114d1a |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01019
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-05
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-03
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05647
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05624
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05548
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-0554
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-13
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-00014
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-02372
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0001
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-0231
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-13022
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-13024
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05573 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76898 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3205
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-52 |
| filingDate |
2009-03-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f077601790644ae43ed3b1aceec587be |
| publicationDate |
2010-09-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2010205921-A |
| titleOfInvention |
Semiconductor device and manufacturing method of semiconductor device |
| abstract |
Provided are a highly reliable semiconductor device and a method of manufacturing the semiconductor device, in which a through wiring is difficult to be disconnected. A first main surface 10A and a second main surface 10B having a first main surface 10A on which an electric circuit 11 is formed and a second main surface 10B opposite to the first main surface 10A. The same as the through hole opening which is the opening of the first main surface 10A of the through hole 10C, the semiconductor substrate 10 having the through hole 10C penetrating through the plurality of conductor wiring layers 12 connected to the electric circuit 11 A multilayer wiring layer 14 having a plurality of interlayer insulating layers 13 having insulating layer openings of the same size at positions, an electrode pad 16 connected to the conductor wiring layer 12 and covering the insulating layer openings, and in the through holes A through wiring layer 19 </ b> A formed and connected to the electrode pad 16, a connection wiring layer 19 </ b> B formed integrally with the through wiring layer 19 </ b> A, and a lead-out wiring layer 19 are provided. [Selection] Figure 3 |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2014519201-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10665538-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-102014891-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2012146754-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20140053912-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2014013810-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I594387-B |
| priorityDate |
2009-03-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |