http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2010118539-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0950e9df7f0e1b73efee1bda859951ad |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76243 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-40117 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-513 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-84 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-792 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4234 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0653 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1203 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-792 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-788 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8247 |
| filingDate | 2008-11-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7fb2e55da27b235254850afe80e06cc4 |
| publicationDate | 2010-05-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2010118539-A |
| titleOfInvention | Nonvolatile semiconductor memory device |
| abstract | PROBLEM TO BE SOLVED: To realize both suppression of a short channel effect and prevention of erroneous writing in a memory cell, and to achieve high performance and low cost of a nonvolatile semiconductor memory device. A non-volatile semiconductor memory device configured by disposing a plurality of non-volatile memory cells on a semiconductor substrate 101. The memory cells are separated from each other on a surface portion of a substrate 101. Provided in the region 120 and the channel region formed between the source / drain region 120 and the buried insulating film 151 having a dielectric constant lower than that of the substrate 101. The first gate insulating film 102, the charge storage layer 103 provided on the first gate insulating film 102, the second gate insulating film 104 provided on the charge storage layer 103, and the second gate insulating film 104 And a control gate electrode 105 provided on the surface. [Selection] Figure 1 |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2016514371-A |
| priorityDate | 2008-11-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 41.