http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2010080056-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36d1d9c59848bff6ad5f55923d1290f5 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-413 |
| filingDate | 2010-01-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f33e9ef533b392bb313a981b7222adaf http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3853d18b100c9a212f6e8e83b476cea0 |
| publicationDate | 2010-04-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2010080056-A |
| titleOfInvention | Static semiconductor memory device |
| abstract | A static semiconductor memory device capable of obtaining a large write margin is provided. In this static semiconductor memory device, internal write signal WLi is set to H level for a predetermined time in response to read / write control signal / WE being set to L level, and internal write signal WLi is set to L. In the case of the level, the power supply voltage VCC is supplied to the memory cell, and in the case where the internal write signal WLi is at the H level, the voltage VCC-VTH obtained by reducing the power supply voltage VCC is supplied to the memory cell. The predetermined time for internal write signal WLi to be at H level is shorter than the time for read / write control signal / WE to be at L level. Therefore, a large static noise margin can be maintained during the non-writing operation, and a large writing margin can be obtained during the writing operation. [Selection] Figure 14 |
| priorityDate | 2010-01-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID7156993 http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID426135032 |
Total number of triples: 13.