| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36d1d9c59848bff6ad5f55923d1290f5 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11807
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0207 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-82
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-822
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3205
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-092
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-52 |
| filingDate |
2008-09-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_92e1709bfd34e850d504de0e4c94adf9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5408f4345f8eaa6a80bce7c5c0858da9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4efba180879f30f471d1a0c4d1d28087 |
| publicationDate |
2010-03-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2010067799-A |
| titleOfInvention |
Manufacturing method of semiconductor integrated circuit device and semiconductor integrated circuit device |
| abstract |
There is provided a circuit layout design method capable of preventing a reduction in circuit reliability even in a circuit cell which has been miniaturized. In order to prevent malfunction caused by the influence of noise from a power supply potential or reference potential having a large potential difference on a gate electrode, a power supply potential or reference potential supplied with a plug connected to the gate electrode is supplied. Among the plugs 6 arranged at equal intervals under the wiring 4 in order to separate the plug 5 from the plug 5 by a sufficient distance that is not affected by noise from the power supply potential or the reference potential. Only the plug 6 arranged at the arrangement position 6A which is not sufficiently separated from the plug 5 (5A) is erased when designing the planar layout. [Selection] Figure 1 |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2018081978-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-5655086-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10043813-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2012053125-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8907492-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9741725-B2 |
| priorityDate |
2008-09-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |