| abstract |
Provided is a technique capable of realizing a highly integrated and high-speed non-volatile memory device in place of an EEPROM or a MONOS type non-volatile memory using polycrystalline silicon as a floating electrode. The memory element section includes a lower electrode 2 formed from the bottom of a connection hole 4 penetrating the interlayer insulating film 3 to a predetermined depth, and a part of the upper surface of the lower electrode 2 exposed to expose the lower electrode 2 A side wall 5 formed on the inner wall of the connection hole 4, a memory element ME formed along the shape of the side wall 5 and electrically connected to the exposed upper surface of the lower electrode 2, and on the memory element ME The upper electrode 6 is formed, and the dimension of the surface where the exposed upper surface of the lower electrode 2 and the memory element ME are connected is made smaller than the minimum processing dimension. [Selection] Figure 9 |