http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2010027678-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_73ebc284a55d5daf0e209d6186c9e65c |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-48091 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-45144 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-48247 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-14 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-73265 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-181 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-15788 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-97 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-12 |
| filingDate | 2008-07-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e316ac8f1916aa5fe08298c89851bd42 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3bc44d351a9bbc22ea1412a0836c977e |
| publicationDate | 2010-02-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2010027678-A |
| titleOfInvention | Manufacturing method of semiconductor device, substrate and manufacturing method thereof |
| abstract | A method for manufacturing a semiconductor device, a substrate, and a method for manufacturing the same, in which the specification of a substrate on which an IC element is mounted can be made common while suppressing an increase in restrictions imposed on the IC element. A substrate having an upper surface and a lower surface facing away from the upper surface, and a plurality of posts arranged side by side so as to form a plurality of columns in a vertical direction and a plurality of rows in a horizontal direction in a plan view. 50, a step of fixing an IC element on the upper surface of the first post 40, a step of electrically connecting the IC element 51 and the upper surface of the second post 40 using a gold wire 53, A step of forming the marks 63a to 63h, including the step of sealing the IC element 51 and the gold wire 53 with the mold resin 61 and the step of arranging the marks 63a to 63h in the outer peripheral region surrounding the plurality of posts 40. Then, the marks 63a to 63h are arranged so that the distance between the marks 63a to 63h and the post 40 closest to the marks 63a to 63h is equal to or an integral multiple of the pitch of the posts 40. [Selection] Figure 13 |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2012047527-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2012069886-A |
| priorityDate | 2008-07-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 28.