http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2010003345-A

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publicationDate 2010-01-07-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2010003345-A
titleOfInvention Semiconductor memory device
abstract The time for a test performed using a reference potential is shortened. In a reference potential precharge of a memory cell array, a bit line BL is selected by turning on a reference potential control transistor SDT whose gate is connected to a reference potential control line SDAL connected to a control circuit 3. Executed. The reference potential precharge of the memory cell array 2 is executed by selecting the bit line BL when the reference potential control transistor SDT whose gate is connected to the reference potential control line SDBL connected to the control circuit 3 is turned on. Reading of information from the selected memory cell and reference potential precharging of the next selected memory cell are performed in an overlapping manner. [Selection] Figure 2
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