| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6b822ee046eb6c45d1e3bd9ce9c1782e |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-19041
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-12044 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02216
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3157
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-97
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-71
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-293 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06K19-07
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06K19-077 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-312
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-822
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-04 |
| filingDate |
2009-05-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_eee9961b51571967dc67c5e29fc67329
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_21747acfb77b0d181ab4dff0d66658d4
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_80e7bf29189a56167beaf9ff8bfac472 |
| publicationDate |
2009-12-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2009302517-A |
| titleOfInvention |
Semiconductor device and manufacturing method of semiconductor device |
| abstract |
An object is to reduce defects in a semiconductor device such as a shape defect and a characteristic defect due to external stress and electrostatic discharge. Therefore, an object is to provide a highly reliable semiconductor device. Another object is to improve the manufacturing yield of semiconductor devices by reducing the defects even during the manufacturing process. A semiconductor integrated circuit sandwiched between an impact resistant layer against external stress or an impact diffusion layer for diffusing the impact, and a conductive layer covering the semiconductor integrated circuit. The conductive layer covering the semiconductor integrated circuit prevents electrostatic breakdown (malfunction of the circuit or damage of the semiconductor element) due to electrostatic discharge (ESD) of the semiconductor integrated circuit. [Selection] Figure 1 |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-106158619-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2013179283-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2016213339-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-112992868-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-112992868-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I703630-B |
| priorityDate |
2008-05-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |