| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_a519e8f8d4dd48a91d9b39a1e25ca97f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0950e9df7f0e1b73efee1bda859951ad
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_8b82d1edd516a3abd718732378965928 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0207
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-41
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823425
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-10 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-76
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8247
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-792
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-788 |
| filingDate |
2008-04-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3545ff6e435164e192e77d002216de8a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d70444295576abf8306a086403a0137e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_43ea85588c73b99adcbfe699caeddfc4
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cfa9769341eee60776a0444e9f32ab4e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e7f177c8df4b90eae3f84e6a00b3367f |
| publicationDate |
2009-10-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2009253144-A |
| titleOfInvention |
Semiconductor device and manufacturing method thereof |
| abstract |
A semiconductor device such as a NAND flash memory capable of suppressing a decrease in breakdown voltage while suppressing a depth of an element isolation region is provided. Gate electrodes PG are arranged side by side on an active area AA between adjacent element isolation films so as to be spaced apart in the gate length direction via a gate insulating film 11. The polycrystalline silicon layer 14 constituting the gate electrode PG has one end portion 14a protruding on the upper surface of the element isolation film located on one side of the active area AA, and the upper surface of the element isolation film positioned on the opposite side of the active area AA. The other end portion 14b projecting upward is provided, and the length L1 of the one end portion 14a and the length L2 of the one end portion 14b are different from each other. [Selection] Figure 4 |
| priorityDate |
2008-04-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |