| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36d1d9c59848bff6ad5f55923d1290f5 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1039
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-26
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1075 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-00 |
| filingDate |
2007-11-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5d44c83e90d03c7c71eac8005fe3e2e2
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3a757dccc043738de60938b6be221828
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5c887fd3e3f1a17d721536fc2de72e2b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7a02d110c4c9da3692c584838c2de707
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_45e84297386ce79c1fc4de0c788c91a1
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_283b2ef5e1b1fe2e1413e52d07ec0b60
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_06331c11044c4b8872b41398f2be6022 |
| publicationDate |
2009-06-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2009123298-A |
| titleOfInvention |
Semiconductor integrated circuit device |
| abstract |
Low latency access is realized even when access requests from a plurality of CPUs compete. A first latch circuit (104) capable of holding an output signal of the X decoder and transmitting it to a word driver (106) is disposed at a subsequent stage of the X decoder (121). A second latch circuit (105) capable of holding the output signal of the Y decoder and transmitting it to the Y selection circuit is arranged at the subsequent stage of the Y decoder (122). A third latch circuit (110) capable of holding the output signal of the sense amplifier and transmitting it to the output circuits (111, 112) is disposed at the subsequent stage of the sense amplifier (108). As a result, a series of processes in reading data stored in the nonvolatile semiconductor memory can be pipelined, and low latency access is possible even when access requests from a plurality of CPUs compete. [Selection] Figure 1 |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8576638-B2 |
| priorityDate |
2007-11-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |