http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2009099747-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0950e9df7f0e1b73efee1bda859951ad |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823857 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823842 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-517 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-49 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-092 |
| filingDate | 2007-10-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ea3d81b60604a9937c82ca1340ce1dc4 |
| publicationDate | 2009-05-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2009099747-A |
| titleOfInvention | Manufacturing method of semiconductor device |
| abstract | PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device including a metal gate MISFET suitable for nMOS and pMOS having different work functions, without the gate insulating film being deteriorated by exposure to the atmosphere or an etching solution for a metal electrode. A method of manufacturing a semiconductor device including an n-type MIS transistor and a p-type MIS transistor having metal electrodes, a gate insulating film provided on a single crystal silicon substrate, and a gate insulating film on the gate insulating film. The first metal film 103, the second metal film 104, the third metal film 105, and the gate electrode 108 including the conductive layer 106 are provided, and the second metal is formed by a thermal process. The constituent elements of the film 104 are diffused into the gate insulating film 102 through the first metal film 103, thereby changing the work function to be suitable for each of the n-type MIS transistor and the p-type MIS transistor. [Selection] Figure 9 |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2012044013-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-5368584-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2011077536-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2011003899-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2009267342-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8552507-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8786031-B2 |
| priorityDate | 2007-10-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 38.