http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2009043332-A

Outgoing Links

Predicate Object
assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_ec3af9072cf2cdc7a99f55c1775f8091
classificationCPCAdditional http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2029-5602
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2029-5006
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-401
classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-025
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-26
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1045
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-02
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4091
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-401
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-56
filingDate 2007-08-08-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4761b572d69e9de2249b1180ffa1117c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_56faabcd489fc8f6aac31c48959eb0ea
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d56a792d81ffcb3a54a6006f8fca4c82
publicationDate 2009-02-26-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2009043332-A
titleOfInvention Semiconductor memory, semiconductor memory test method and system
abstract PROBLEM TO BE SOLVED: To detect and repair a memory block defect without increasing a chip size. Each program circuit outputs an operation specification signal indicating a first or second operation specification according to a program state. Each specification change circuit is set by a corresponding block selection signal and outputs an operation specification signal indicating the second operation specification. Each timing control circuit changes the output timing of the precharge control signal for the bit line according to the operation specification signal. A failure can be detected for each memory block before the program circuit is programmed by the operation specification signal from the specification change circuit. Thereafter, the defect can be relieved by the program circuit. The output timing of the precharge control signal can be set for each memory block by a block selection signal without wiring a dedicated signal line for setting each specification changing circuit. For this reason, an increase in chip size can be minimized. [Selection] Figure 4
priorityDate 2007-08-08-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

Incoming Links

Predicate Subject
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2004234729-A
isDiscussedBy http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID425965024
http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID414861297
http://rdf.ncbi.nlm.nih.gov/pubchem/gene/GID734313
http://rdf.ncbi.nlm.nih.gov/pubchem/gene/GID56882
http://rdf.ncbi.nlm.nih.gov/pubchem/gene/GID56990
http://rdf.ncbi.nlm.nih.gov/pubchem/gene/GID444029
http://rdf.ncbi.nlm.nih.gov/pubchem/gene/GID594923
http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID3081143
http://rdf.ncbi.nlm.nih.gov/pubchem/gene/GID447222
http://rdf.ncbi.nlm.nih.gov/pubchem/gene/GID72729
http://rdf.ncbi.nlm.nih.gov/pubchem/gene/GID57912
http://rdf.ncbi.nlm.nih.gov/pubchem/gene/GID447104
http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID7216

Total number of triples: 35.