http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2009026778-A

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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-288
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C23C18-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
filingDate 2007-07-17-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5d9abc64422291c8cff265760a7109d9
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publicationDate 2009-02-05-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2009026778-A
titleOfInvention Substrate processing method
abstract Contact wiring can be continuously formed by electroless plating inside via holes of different depths, and the contact wiring (plating film) is prevented from bumping up on the surface of an insulating film. A substrate having a first via hole and a second via hole deeper than the first via hole is prepared inside an insulating film laminated on a semiconductor substrate, and the first via hole and the second via hole are provided inside the first via hole and the second via hole, respectively. Contact wiring is formed by the first electroless plating in which the substrate surface is in contact with the plating solution until the first via hole is almost filled, and then the relative speed between the substrate surface and the plating solution flowing along the surface is increased. Then, second electroless plating is performed while suppressing the growth of the plating film formed on the surface of the contact wiring formed in the first via hole. [Selection] Figure 2
priorityDate 2007-07-17-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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