http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2008505386-A
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-355 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-362 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0623 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-34 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-02 |
| filingDate | 2005-06-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2008-02-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2008505386-A |
| titleOfInvention | Data processing device and compatible processor |
| abstract | A processor capable of maintaining backward compatibility with previous generation processors is provided. When the current generation processor 100 writes a value on the address where the 0th area access cycle number register is arranged in the previous generation processor 500, the same value is written to the 0th area random access cycle number register 170, and The value of the 0th area page size register 190 is set to 0 (page size = 0 bytes), and page mode access is not performed. When the current generation processor 100 writes a value on the address where the first and second area access cycle number registers are arranged in the previous generation processor 500, the same value is stored in the first area random access cycle number register 171 and the first area access cycle number register 171. The two area random access cycle number register 172 is written, and the values of the first area page size register 191 and the second area page size register 192 are set to 0, and the page mode access is not performed. |
| priorityDate | 2004-07-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 23.