http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2008277475-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6b822ee046eb6c45d1e3bd9ce9c1782e |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234 |
| filingDate | 2007-04-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_da845e0c0666703c36355238b8206e91 |
| publicationDate | 2008-11-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2008277475-A |
| titleOfInvention | Method for manufacturing semiconductor device |
| abstract | An object of the present invention is to provide a semiconductor device having a novel structure for realizing low voltage operation and low power consumption of an integrated circuit and a method for manufacturing the semiconductor device. An island-shaped semiconductor layer is formed, a first insulating layer is formed on the semiconductor layer, the first insulating layer is selectively etched to locally expose the semiconductor layer, and the exposure is performed. The surface of the semiconductor layer is etched to locally thin the semiconductor layer, and the second insulating layer is formed on the thinned region and the remaining first insulating layer. A conductive layer is formed on the conductive layer, and a third insulating layer is formed on the conductive layer by a coating method. The third insulating layer and the conductive layer are etched at substantially the same etching rate until the second insulating layer formed on the first insulating layer or the first insulating layer is exposed, so that the thin film of the semiconductor layer A gate electrode is formed by leaving the conductive layer in the converted region. The first insulating layer and the second insulating layer are etched using the gate electrode as a mask. [Selection] Figure 1 |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111095177-A |
| priorityDate | 2007-04-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 52.