| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36d1d9c59848bff6ad5f55923d1290f5 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01004
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01006
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01005
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01033
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-1306
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01028
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01074
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01015
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01079
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01014
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01013
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01022 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-05
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-03 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-60
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3205
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-52 |
| filingDate |
2006-12-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_07f2de96e9815fa8ecd4a2b689b39142
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cbbc4bca11ecba3ece86455e6100eeab |
| publicationDate |
2008-06-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2008140952-A |
| titleOfInvention |
Manufacturing method of semiconductor device |
| abstract |
The manufacturing yield of a semiconductor device having a pad electrode on the surface is improved. A vertical MISFET having a trench gate structure is formed on a semiconductor substrate, a gate wiring and a source wiring are formed, and then a top surface protective film is formed by a spin coating method. Then, a resist pattern RP1 having an opening 28a at a position where a gate pad electrode is to be formed is formed on the surface protective film, and the surface protective film is etched using the resist pattern RP1 as an etching mask to form an opening 29a in the surface protective film. To do. A gate pad electrode is formed by the gate wiring exposed from the opening 29a. The planar shape of the opening 28a of the resist pattern RP1 is based on a quadrangular shape, but the portion closest to the corner 44a of the semiconductor device region 10A to be a semiconductor chip later is rounded to provide the corner 44a. The shape is retracted in the direction away from the center. [Selection] Figure 16 |
| priorityDate |
2006-12-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |