http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2008123543-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_d231147f38595bbe3114b758cba4a298 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-16 |
| filingDate | 2007-12-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c9254236785e03a6d452bb874cc5dc88 |
| publicationDate | 2008-05-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2008123543-A |
| titleOfInvention | Data transmission method, system and device |
| abstract | A memory system capable of realizing a high-speed operation between a memory controller and a memory module. In a memory system including a memory controller and a memory module equipped with a DRAM, a buffer is mounted on the memory module, and the buffer and the memory controller are connected with data wiring, command / address wiring, and clock wiring. The DRAM on the memory module and the buffer are connected by an internal data line, an internal command / address line, and an internal clock line. Data wiring, command / address wiring, and clock wiring may be connected in cascade with buffers of other memory modules. Data transmission is performed at high speed between the DRAM and the buffer on the memory module using a data phase signal synchronized with the clock. [Selection] Figure 1 |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2018012397-A |
| priorityDate | 2002-08-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 16.