http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2008112513-A

Outgoing Links

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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-407
filingDate 2006-10-31-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_32ea80707b3f4b19bf075a6b9e19bee9
publicationDate 2008-05-15-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2008112513-A
titleOfInvention Semiconductor memory device
abstract Leakage current in a standby state is suppressed. In a semiconductor memory device having a plurality of word lines, bit lines, and memory cells arranged at intersections thereof, a word driver circuit for driving the word lines includes a first node and a second node. And a driving PMOS transistor and a driving NMOS transistor, which are connected in series and connected to a third node at the gate, and a word line is connected to a connection node of both transistors. A first voltage or a second voltage lower than the first voltage is applied to the third node, and a first voltage or a second voltage is applied to the first node. Further, a leakage preventing NMOS transistor is provided between the third node and the gate of the driving PMOS transistor, the first voltage being applied to the gate or a voltage in the vicinity thereof. [Selection] Figure 4
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2010187162-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8358535-B2
priorityDate 2006-10-31-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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Total number of triples: 21.