http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2008102797-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36d1d9c59848bff6ad5f55923d1290f5 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-04 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-15 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-131 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-14 |
| filingDate | 2006-10-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_32acf9dd36b01929ac96c252ae9a1167 |
| publicationDate | 2008-05-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2008102797-A |
| titleOfInvention | Semiconductor device, semiconductor integrated circuit device, and allowable phase difference measurement circuit |
| abstract | A semiconductor device capable of effectively suppressing a current peak at low cost is obtained. In step ST1, the clock phases of module A21 and module B22 are made to coincide with each other, and then in step ST2, data is transferred from module A21 to module B22. Thereafter, in step ST3, the clock phase difference between the clock CLKA of the module A21 and the clock CLKB of the module B22 is set to a predetermined magnitude, and then in step ST4, the module A21 and the module B22 are each independently subjected to predetermined arithmetic processing. I do. In step ST5, the phases of the clock CLKA of the module A21 and the clock CLKP of the CPU 25 are matched, and then the calculation result of the module A21 is read by the CPU 25 in step ST6. [Selection] Figure 16 |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2012085190-A |
| priorityDate | 2006-10-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 36.