http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2008066598-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fd83260a96356882b5f50dd097411a72 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F30-367 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8244 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8242 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108 |
| filingDate | 2006-09-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c850e5b85a13abefd95f5782b16351e6 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6006c2b55197972818035e10302fbb0c http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3eedc00baf3a3e9a1c665786a27e193a |
| publicationDate | 2008-03-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2008066598-A |
| titleOfInvention | Soft error rate calculation method, program, semiconductor integrated circuit design method and design apparatus, and semiconductor integrated circuit |
| abstract | Provided is a method for easily estimating a soft error rate (SER) of an SRAM or a memory circuit element at a product design stage. A measurement result obtained by measuring a relation between an information storage node diffusion layer area and a soft error rate (SER) of a storage circuit constituted by a MISFET or an information holding circuit using a plurality of information storage node voltages Vn as parameters is used. (S1) A first mathematical expression representing the dependency of SER on the information storage node area at the same information storage node voltage Vn is derived (S2). Then, from the measurement result, the relationship of the SER information storage node voltage dependence in the same information storage node area Sc is substituted into the first formula to derive the second formula (S3). The SER can be calculated by substituting the information storage node area and the information storage node voltage of the storage circuit or information holding circuit to be obtained into the second equation (S4). [Selection] Figure 5 |
| priorityDate | 2006-09-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 25.