http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2008052811-A

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0950e9df7f0e1b73efee1bda859951ad
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-792
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-788
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8247
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-06
filingDate 2006-08-24-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ea889fc8a0a2571496b4b8ced772efa7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_81ff72c1a2536a1cc8f1e596e5d4fbf7
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publicationDate 2008-03-06-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2008052811-A
titleOfInvention Nonvolatile semiconductor device
abstract A semiconductor memory device in which erroneous writing and erroneous erasing to a memory cell due to miniaturization is reduced is provided. MCm1 includes memory cells MC11 to MC1n,..., MCm1 in which a charge storage layer and a control gate layer are laminated on a channel via an insulating film, and a diffusion layer that forms a current path is provided across the channel. In a nonvolatile semiconductor device having bit lines BL1 to BLn arranged in a matrix and having bit lines BL1 to BLn connected to diffusion layers of a plurality of memory cells MC11 to MC1n,. Transistors TR1 to TRn that are connected and discharge a voltage higher than a predetermined value applied to the diffusion layers of the memory cells MC11 to MCmn are provided. The drains of the transistors TR1 to TRn are connected to the bit lines BL1 to BLn, and the sources are grounded. Each transistor TR1 to TRn has a predetermined threshold and is diode-connected. [Selection] Figure 1A
priorityDate 2006-08-24-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 18.