http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2007324540-A

Outgoing Links

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_158f76bc9c383ac988486428cf8eb47e
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-739
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
filingDate 2006-06-05-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_85d49cd4a2d898e6713638c83e39c8ab
publicationDate 2007-12-13-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2007324540-A
titleOfInvention MOS type semiconductor device and manufacturing method thereof
abstract [Objective] Even without adopting a trench gate structure, the trade-off relationship between on-state voltage and turn-off loss is further improved, and excessive polishing and over-polishing are prevented to suppress variation in on-voltage and to improve gate characteristics. To provide a MOS type semiconductor device having a gate structure. [Structure] A first insulating film having a first opening on a surface of a one-conductivity type semiconductor substrate, a substrate insulating film provided in the first opening and being thinner than the first insulating film, and a substrate insulating film A top gate structure comprising: a second opening provided; and a one-conductivity-type deposited semiconductor layer stacked on the substrate insulating film and having a thickness similar to that of the first insulating film in the first opening. The MOS type semiconductor device is a MOS type semiconductor device in which the interval between the first insulating films sandwiching the first opening is 25 μm or less. [Selection] Figure 1
priorityDate 2006-06-05-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

Incoming Links

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Total number of triples: 20.