http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2007300131-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0950e9df7f0e1b73efee1bda859951ad |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3205 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-82 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-52 |
| filingDate | 2007-06-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e79df52b64bfbcf693fe228e8530427f http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_686c548b2a828caaf974a3177d24c4df |
| publicationDate | 2007-11-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2007300131-A |
| titleOfInvention | LSI wiring structure design method |
| abstract | PROBLEM TO BE SOLVED: To provide an LSI wiring structure design method capable of reducing wiring capacitance C and wiring delay RC. An estimate the process variation amount and [delta] P, and sets the allowable value of variation in the interconnect delay Δ (RC) / (RC) and xi] RC, a fringe capacitance ratio from fringe capacitance C F and parallel-plate capacitor C P by evaluating F = C F / C P, the following equation F ≦ (1-δ P) · δ P / (δ P -ξ RC) - 1 The wiring structure is determined so as to satisfy the above. [Selection] Figure 1 |
| priorityDate | 1999-06-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 19.