http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2007295089-A
Outgoing Links
Predicate | Object |
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assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38520f366e74704305b34fb93a81121e http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6dd74b20fbf2e0ebf10c7bfad4f6c8c5 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6c17cc295437cecaed9912b45ce4eeb2 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_d225c23659cbc58c4a541ac45a16ffe5 |
classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03M13-15 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L1-00 |
filingDate | 2006-04-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fd17c3c33ad57ed10f63e9fa970c2472 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e3bf51381f00c1261ec66b8713f894d0 |
publicationDate | 2007-11-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber | JP-2007295089-A |
titleOfInvention | Error correction decoding circuit |
abstract | An error correction decoding circuit with high processing reliability and short processing time is provided. An FEC input phase control circuit extracts a predetermined number of bytes from a frame and stores the parity in a storage circuit and generates signals Tin, Tout, and S0. After receiving the signal Tin, the RS input phase control circuit 150 outputs data by predetermined bytes from the frame output from the delay circuit 110, and further reads out and outputs the corresponding parity from the storage circuit 140. The RS decoders 161-0 to 161-2 perform error correction decoding processing using data and parity. The FEC output phase control circuit 170 receives a frame from the delay circuit 120 at the reception timing of the signal Tout and receives corrected data from the FEC arithmetic circuit 160. When the signal S0 indicates normality of the received frame, the FEC output phase control circuit 170 replaces the frame data. When the corrected data is output and the signal S0 indicates abnormality, the frame data is output as it is. [Selection] Figure 1 |
isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-4677639-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2007295090-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-103155418-A |
priorityDate | 2006-04-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 40.