http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2007288204-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_80787665b837ed3eb503bbcd27c0043a |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-04 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-26 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-092 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-822 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8244 |
| filingDate | 2007-05-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_553f9d4b6bbe430eb3c52261b352f20b http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_252fa70a86037c86e90d6ef7806f76e6 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_50150c8b854d79d51cbedda695c0b84f http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bf1217e98137eb26614028b6e88bd456 |
| publicationDate | 2007-11-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2007288204-A |
| titleOfInvention | Semiconductor integrated circuit device |
| abstract | The layout efficiency of a semiconductor integrated circuit device is improved. An n-type well 2 in which one transistor Tp constituting a CMOS circuit is arranged and a power supply voltage line Vdd are electrically connected via a switching transistor Tps and the other constituting the CMOS circuit is connected. The p-type well 3 in which the transistor Tn is disposed and the power supply voltage line Vss are electrically connected via the switching transistor Tns. When testing the semiconductor integrated circuit device, the switching transistors Tps and Tns are turned off, and a potential suitable for the test is supplied from the outside to the n-type well 2 and the p-type well 3 to cause thermal runaway caused by the leakage current. In the normal operation of the semiconductor integrated circuit device, the switching transistors Tps and Tns are turned on to set the n-type well 2 and the p-type well 3 to the power supply voltages Vdd and Vss, respectively, thereby preventing latch-up. [Selection] Figure 1 |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-101795753-B1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2011511440-A |
| priorityDate | 1995-12-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 25.