| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_be92719b856db86c092cc233e9512ca2 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7835
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7833
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1083
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6659
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66659
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42368
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823412 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823892
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823814
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0922
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823418 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-092
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-822 |
| filingDate |
2006-03-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7beb038110635c59efbfd4ff92ce23ae |
| publicationDate |
2007-09-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2007251082-A |
| titleOfInvention |
Semiconductor device including MOS transistor having LOCOS offset structure and manufacturing method thereof |
| abstract |
A high-breakdown-voltage LOCOS offset transistor configured to eliminate off-leakage current without providing an LDD region and a normal low-voltage transistor configured to eliminate LD-region and eliminate off-leakage current are efficiently manufactured on the same semiconductor substrate. To do. A semiconductor device having at least one LOCOS offset transistor (29, 31) and at least one normal transistor (15, 17) mounted on a semiconductor substrate (1), the LOCOS offset transistor comprising a channel and a source, and The transistor does not have an LDD region between the channel and the drain, and a normal transistor has an LDD region between the channel and the source and between the channel and the drain. The LDD region is composed of two types of low-concentration diffusion layer regions having different conductivity types. By not providing the LDD region in the LOCOS offset transistor and providing the LDD region in the normal transistor, both of the off-leakage currents can be eliminated. [Selection] Figure 1 |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2012134284-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2013145792-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9129841-B2 |
| priorityDate |
2006-03-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |