http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2007172813-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6b822ee046eb6c45d1e3bd9ce9c1782e |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-412 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-41 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8244 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-10 |
| filingDate | 2006-11-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f9854e3e445238b3183f194c11719fac http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_84dbc201e08533fc82801dce845135b0 |
| publicationDate | 2007-07-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2007172813-A |
| titleOfInvention | Semiconductor memory device and operation method of semiconductor memory device |
| abstract | When manufacturing an SRAM in a situation where transistor characteristics such as TFTs vary, or in a situation where power is supplied from an RF circuit and the power is not stable, a conventional memory cell structure with six transistors in a memory cell at the time of reading is used. Incorrect writing that rewrites the value held by. An SRAM memory cell separates a writing circuit and a reading circuit, thereby preventing erroneous writing of the SRAM and enabling stable operation. In addition, an SRAM is provided that can perform a writing operation more reliably without causing erroneous writing by considering the writing timing. [Selection] Figure 1 |
| priorityDate | 2005-11-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 40.