http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2007171965-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2320-0276 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-027 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-36 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G02F1-133 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3688 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-20 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-20 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G02F1-133 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-36 |
| filingDate | 2006-12-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_86c06f65fcbb68c044108579c67d9d49 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_67567c877779a2923887a1d50046ade4 |
| publicationDate | 2007-07-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2007171965-A |
| titleOfInvention | Driving integrated circuit of liquid crystal display device having double column structure |
| abstract | A driving integrated circuit of a liquid crystal display device having a double column structure is provided. A driving integrated circuit of a liquid crystal display device includes a first shift register unit, a first data latch unit, first and second decoders, and first and second output buffers. The first data latch unit receives and stores the first and second group channel data in response to the clock signal generated from the first shift register unit. The first and second decoders receive first and second group channel data, respectively, and output corresponding gamma voltages. The first and second output buffers are respectively disposed along one long side of the integrated circuit chip, and drive the corresponding channel by buffering the gamma voltage. The first shift register unit and the first data latch unit are shared by the upper and lower blocks and can process the first and second group channel data in common. [Selection] Figure 4 |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2011133543-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2012215602-A |
| priorityDate | 2005-12-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 49.