| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1027
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1066
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1045
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4076
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4094 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-407
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4091
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4076 |
| filingDate |
2006-11-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9b66f16a8151f7f94dbe906947770ef9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0c4ffcad77f6dcfb9a703477f0226ce1
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_daead64360af78d50b078ccaab392e8b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e4717f4482edeb73066e6d0d606a09da
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9b059572a51d1b1efbb24f86cabe7e01 |
| publicationDate |
2007-06-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2007141439-A |
| titleOfInvention |
Latency control circuit and method thereof, and automatic precharge control circuit and method thereof |
| abstract |
A latency control circuit and method thereof, and an automatic precharge control circuit and method thereof are provided. A plurality of slaves comprising: a master unit that activates at least one reference signal based on the reference signal and an internal clock signal; and a plurality of slave units that receive at least one master signal and a plurality of signals. Each of the units is a latency control circuit that generates an output signal based on at least one of a plurality of received signals. A precharge command delay unit for generating a plurality of first precharge command delay signals in response to a write auto precharge command signal and an internal clock signal, and at least one bank address delay unit for generating a delayed bank address signal And a precharge main signal generator for outputting a precharge main signal based on the delayed bank address signal. [Selection] Figure 2 |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2012108979-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8040747-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2013206474-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9142276-B2 |
| priorityDate |
2005-11-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |