http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2007096358-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0950e9df7f0e1b73efee1bda859951ad |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8247 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-792 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-788 |
| filingDate | 2007-01-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_aa4de649a3f15238c85f908d9ff7aa84 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9c3fded2670238637beb4c6baa04c6f1 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6d137eb616dda8079e13be52125a06b9 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5580566b600297187fe8e587d8f7de85 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_dce9181fcf481d71197f89a40e747626 |
| publicationDate | 2007-04-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2007096358-A |
| titleOfInvention | Manufacturing method of semiconductor memory device |
| abstract | PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor memory device capable of minimizing interference between adjacent cells even when miniaturization advances and the distance between cells is reduced. A cell portion gate insulating film and a first conductive layer are formed on a surface of a semiconductor substrate, such that an upper end face of the first conductive layer is lower than a position of an upper end face of an element isolation insulating film. The steps of realizing the sequentially laminated structure and the conductive interlayer insulating film 8 a made of an insulating film having a relative dielectric constant larger than that of the silicon oxide film are separated from each other by the element isolation insulating film 7. Conductive interlayer insulation of each memory cell column so that the bottom surface of the second conductive layer 10 is in contact with the upper end face of the element isolation insulating film 7 so as to be a wiring common to the memory cell column and the step of arranging on the top portion Placing on the film 8a. [Selection] Figure 1 |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2014175480-A |
| priorityDate | 2007-01-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 47.