http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2007095277-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1a492183be65153abfa7dec00d51c816 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-40622 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-406 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-40618 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-40615 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-406 |
| filingDate | 2006-09-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_acd50a8e9b89165f5caba5f75fe19c00 |
| publicationDate | 2007-04-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2007095277-A |
| titleOfInvention | Semiconductor memory device |
| abstract | A semiconductor memory device that reduces the consumption of peak current during a refresh operation of a low-power semiconductor memory device having a plurality of banks is provided. In response to a plurality of banks, an EMRS unit including the bank-specific refresh information, and the bank-specific refresh information, at least two or more banks are refreshed sequentially by unit bank. A semiconductor memory device comprising a bank refresh controller for supporting a refresh operation. [Selection] Figure 3 |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8675436-B2 |
| priorityDate | 2005-09-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID23676225 http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID452193847 |
Total number of triples: 17.