| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fd83260a96356882b5f50dd097411a72 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M9-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-0175
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L25-02 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L25-03
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-156
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03M9-00 |
| filingDate |
2005-07-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_195d0383f923be020c78e73dd6e5ced7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8bb9e1663533774fcf61a0d80af4bb2d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_61117cd41463d637812e700dc5eced2d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_01f0da32c37a34837fb0e0fa74848037
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a13709266ccd499fcb2b1112fe03be1d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9af1bd14a564641f550fbefc897bd6bb
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d6dbfabb4ec4bf4df64bd6fc3424da64 |
| publicationDate |
2007-02-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2007036870-A |
| titleOfInvention |
Pre-emphasis circuit |
| abstract |
【Task】 Provision of pre-emphasis circuits that can reduce current consumption, circuit scale, and high-speed operation. [Solution] A first parallel-to-serial converter 101 1 for converting parallel data to first serial data, and a second parallel-serial conversion circuit 101 2 for converting the parallel data into second serial data, said first and second A mixing circuit 103 for inputting first and second serial data of two parallel serial conversion circuits and outputting a signal in which a change point of the first serial data is emphasized; and the first and second parallel serial conversions The circuit includes a first clock group composed of clock groups different from each other and a clock generation circuit 102 supplying a second clock group composed of clock groups different from each other. The first phase clock corresponds to the second phase clock of the first clock group. [Selection] FIG. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-102292736-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2022173098-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2009171578-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2012142902-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2014183571-A |
| priorityDate |
2005-07-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |