http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2006515972-A
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L1-1819 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L1-16 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04B7-005 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L1-005 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L1-1854 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L1-0066 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L1-1835 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04W4-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04B7-005 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L1-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L29-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L1-18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L1-16 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04W80-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L29-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04B7-26 |
| filingDate | 2004-01-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2006-06-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2006515972-A |
| titleOfInvention | Output buffer control apparatus and method in complex retransmission mobile communication system |
| abstract | An output buffer control apparatus and method for transmitting data decoded by a channel decoder with a processor while reducing a load. The apparatus of the present invention includes a high-speed turbo decoder that decodes packet data received on a packet data channel using information received on a forward packet data control channel and outputs buffer information of the decoded data; A buffer for receiving and storing data, an interrupt signal for receiving data information and buffer information decoded from the decoder, and reading data stored in the buffer using the received data information and buffer information; and An output buffer controller for generating a read address; and a processor for reading data stored in the output buffer according to the read address received when the interrupt signal is received from the output buffer controller. |
| priorityDate | 2003-01-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 28.