http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2006166460-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_9985d583b30ac1151ed99d3b3cbc1985 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-17744 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-0175 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-177 |
| filingDate | 2005-12-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_155c0915bc92c7d07e44160576d6c309 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_89ea1b76897d1ee3562507b470dad96a |
| publicationDate | 2006-06-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2006166460-A |
| titleOfInvention | Techniques for implementing hardwired decoders with differential input circuits |
| abstract | Techniques for improving signal timing of differential input / output (IO) circuits on a programmable logic integrated circuit are provided. A differential buffer receives a differential signal applied to a differential input pin. The output signal of the differential buffer is routed to two hard IO decoder blocks located in two adjacent rows / columns of programmable logic elements. Each IO decoder block has a data-in register that receives the output signal of the differential buffer. Data-in registers in two adjacent IO decoder blocks support double clocking techniques. The IO decoder block of the present invention has reduced setup time, reduced hold time, reduced sampling window, and minimal impact on die area compared to soft DDIO blocks. [Selection] Figure 1 |
| priorityDate | 2004-12-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 47.