| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0950e9df7f0e1b73efee1bda859951ad |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0425 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B69-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-41
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-40 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8247
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-792
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-788 |
| filingDate |
2004-10-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_de2be1b3d3e818e885b9a69f0207791d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a42634b2959292aec80ae61f1e0f0efa |
| publicationDate |
2006-04-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2006114140-A |
| titleOfInvention |
Nonvolatile semiconductor memory device and control method thereof |
| abstract |
A nonvolatile semiconductor memory device capable of improving read operation reliability and a control method thereof. A nonvolatile semiconductor memory device includes a first cell array in which first memory cells having floating gates are arranged in a matrix, a second cell array including a plurality of second memory cells having floating gates, and a first memory. A first bit line connected to the drain of the cell, a second bit line connected to the drain of the second memory cell, a first precharge circuit for precharging the first bit line, and reading from the first memory cell A sense amplifier that amplifies the data, a second bit line is precharged and discharged during a read operation, and the first precharge circuit and the sense are sensed based on the time required to precharge and discharge the second bit line. And a read control circuit for controlling the amplifier. [Selection] Figure 4 |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-109801657-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-109801657-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2018526762-A |
| priorityDate |
2004-10-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |