| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0950e9df7f0e1b73efee1bda859951ad |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-26
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B69-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-35
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-105
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-49
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-41
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-40 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-792
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-788
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8247 |
| filingDate |
2004-10-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_de2be1b3d3e818e885b9a69f0207791d |
| publicationDate |
2006-04-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2006114125-A |
| titleOfInvention |
Nonvolatile semiconductor memory device |
| abstract |
To provide a nonvolatile semiconductor memory device capable of improving the reliability of a memory cell. A non-volatile semiconductor memory device includes a plurality of memory cells including a first MOS transistor MT having a charge storage layer and a control gate, and a second MOS transistor ST having a drain connected to the source of the first MOS transistor MT. Are arranged in a matrix, a word line WL that commonly connects the control gates of the first MOS transistors MT in the same row, and a select that commonly connects the gates of the second MOS transistors ST in the same row. Switch elements D0 to D (4m−) electrically connecting the gate line ST and the semiconductor substrate 202 on which the memory cell array 10 is formed and the select gate lines SG0 to SG (4m−1) during the erase operation. 1). [Selection] Figure 2 |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2009076188-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2016525764-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11295812-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10438661-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2009245527-A |
| priorityDate |
2004-10-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |