| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5769454532deecf82d863abdfffeaf9b |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K3-38
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K3-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K3-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K3-20 |
| filingDate |
2004-09-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_682963110d7d8b361c05173ec145989e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b8f3fdb0d25af85c4c073d65cdff88c7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_33f8a46ba440ff56c0ec16b1c7764068
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_03d5ed9023b9ea2261db7dc5ad465f0f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9c54970a4fa9a04a7619197453e7ca81 |
| publicationDate |
2006-04-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2006108129-A |
| titleOfInvention |
Circuit board manufacturing method and circuit board |
| abstract |
A method of manufacturing a circuit board and a circuit board capable of reducing the specific resistance value of a circuit pattern and using an insulating substrate made of a material having a low heat-resistant temperature are provided. The step of forming a resin-containing circuit pattern 40a-1 on the surface of an insulating substrate 30-1 and the metal fine particles present in the paste are fused to the transfer surface 65-1 of the transfer member 60-1. Forming the fused circuit pattern 70a-1 and the resin-containing circuit pattern 40a-1 and the fused circuit pattern 70a-1 were previously formed on the resin-containing circuit pattern 40a-1. The step of laminating through the conductive adhesive coating 90-1 and the separation member 60-1 are separated to form the fused circuit pattern 70a-1 on the transfer surface 65-1 of the transfer member 60-1 on the insulating substrate 30-1. Forming a circuit pattern formed by laminating the resin-containing circuit pattern 40a-1 and the fused circuit pattern 70a-1 on the insulating substrate 30-1. [Selection] Figure 2 |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2007324426-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2015207445-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2016536810-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2010183082-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2019123629-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9578752-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10219388-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-102045113-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-106538075-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-WO2019123629-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20160102166-A |
| priorityDate |
2004-09-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |