| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_be055db3c1a09879df07379ba969e223 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-417
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-413 |
| filingDate |
2004-06-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fffa437a52949005538a8abffd0cba49
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_71cfa2b1e93c69649acc586fefdba7af |
| publicationDate |
2006-01-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2006004463-A |
| titleOfInvention |
Semiconductor memory device |
| abstract |
Since write end timing is generated by a read delay, an excessive timing margin is included in a write operation, which hinders an increase in cycle time. A dummy word line and a timing adjustment circuit having a delay characteristic substantially equal to a normal write delay characteristic are provided. The timing adjustment circuit 5 includes a dummy cell 6 driven by a dummy word line DWL and a detection circuit 7 that detects an output of the dummy cell 6. The write operation can be terminated based on a detection signal output by detecting a normal write delay, and an excessive timing margin in the write operation can be suppressed. [Selection] Figure 1 |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8451672-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100947522-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2008226404-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-109697996-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-109697996-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2012160257-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7656733-B2 |
| priorityDate |
2004-06-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |