http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2005539333-A
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3885 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3824 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3826 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3891 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3875 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-38 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-30 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-38 |
| filingDate | 2003-09-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2005-12-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2005539333-A |
| titleOfInvention | Fully synchronous super pipelined VLIW processor system and method |
| abstract | The present invention relates to a method of fabricating a fully synchronous super pipelined VLIW processor that produces not only high performance processors but also high frequency operating processors. It is proposed to divide the operating unit of the VLIW into two subsets. The first subset unit performs a basic loop that includes only a single register delay in the loop, while other units connected around the first unit have a conventional delay in the loop. |
| priorityDate | 2002-09-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID44152182 http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID426271163 |
Total number of triples: 18.