http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2005348168-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_be055db3c1a09879df07379ba969e223 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-15 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-00 |
| filingDate | 2004-06-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_77807d8b46f40f3d4091b57f93d16ba4 |
| publicationDate | 2005-12-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2005348168-A |
| titleOfInvention | Clock control device |
| abstract | PROBLEM TO BE SOLVED: To provide a clock control circuit capable of controlling a phase relationship accurately at high speed when a multiphase external clock is inputted and a frequency dividing circuit is operated by the input clock. The delay time of each D flip-flop is handled by treating the frequency-divided signal generated by dividing the multi-phase clock (CLK11 to CLK14) inputted externally as data and clock of the downstream D flip-flop. Only the setup time of the D flip-flop is an element that determines the frequency of the clock, and this setup time is further provided with a margin by the delay buffers (111 to 115), thereby enabling higher frequency clock control. To do. [Selection] Figure 1 |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8120392-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-1811664-A2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-1811664-A3 |
| priorityDate | 2004-06-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 35.